| 摘要 |
<p>PURPOSE:To provide a NAND cell type EEPROM in which bit line voltage applied to a bit line and selective gate voltage are made lower without causing erroneous writing upon writing data, and in which high performance and high integration are ensured. CONSTITUTION:In a NAND cell type EEPROM, a relationship among bit line voltage VMbit, selective gate SG1 voltage VMC, and a threshold value Vth of a select transistor is set to satisfy VMbit>VMG-Vth upon writing data such that source and drain diffusion layers of a nonwritten cell M8 connected with the same control gate CG4 as a written cell M4 are not electrically connected with a potential of a bit line BL2. Further, data writing time is set to be a time 10 ms or shorter there is changed a threshold value in the written cell M4 where the source and drain diffusion layers are electrically connected with the bit line BL2 while there is not changed the threshold value on the nonwritten cell M8 where the diffusion layers are not electrically connected with the bit line BL2.</p> |
