Digital multiplier circuit for integer values - has numbers encoded into logarithmic values that are added together and decoded to obtain antilogarithm

摘要

The digital multiplication circuit for use with integer numbers receives the two input values at the encoding stages in order to generate logarithmic values (SE1). The unit employs segment coding to fix the highest value exponents, with an 'n' bit matrix to effect linearisation. The values are then applied to adder stages (St 2) that use a carry select process to improve the speed of operation. The outputs from the adders are fed to a third stage (St 3) that carries out an antilogarithmic function to obtain the product value. USE/ADVANTAGE - for signal processing, partic. real=time e.g. neural networks, HDTV. Simplified integer multiplication, reduced chip area required.