Discretionary lithography for integrated circuits.

摘要

Large scale integrated circuits are fabricated using redundant circuit elements to replace defective circuit elements by discretionary interconnect changes as determined by fine-grain testing of the integrated circuits after the logic units (such as individual transistors or logic gates) are fabricated and before they are electrically interconnected. The redundant circuit elements are then interconnected to non-defective circuit elements by one of two methods. In the first method a stepper-scanner apparatus modified to expose most of a resist layer defines the interconnect circuitry, but is shuttered-off over the discretionary interconnect changes. Then the discretionary interconnect changes are exposed by a conventional direct write on wafer pattern generation apparatus. In the second method, the interconnect patterning is accomplished by first fabricating a fixed custom mask defining the interconnect layer for a particular lot size (such as 100) of wafers. The fixed mask is fabricated after each wafer of the lot has been tested, and incorporates all the discretionary changes required to avoid interconnection to each defective circuit element in each of the wafers. The fixed custom mask is then used to expose the resist layer defining the interconnect circuitry for each of the 100 wafers.