| 摘要 |
<p>PURPOSE:To prevent fault due to non-coincidence in phase between a frequency dividing clock signal generated in respective common device, as to a phase synchronizing system in a duplicated common device generating the frequency dividing clock from a clock signal supplied from a duplicated host device and supplying it to lower-order devices. CONSTITUTION:Frequency dividing clock generation means 301 counting the clock signal supplied from respective host devices 100 and generating the frequency dividing clock signal at a prescribed period, is respectively provided. In a duplicated common device 300 in which any one of the means currently operating as a current system supplies the frequency dividing clock signal to the lower-order devices 200, comparison means 302 comparing the phase of the frequency dividing clock signal generated by itself with that of the frequency dividing clock signal generated by the other common device and notifying the host device of whether or not the preliminarily set value is exceeded by the phase difference is provided for the respective common device and switchover between current device/spare device is stopped.</p> |
