发明名称 OPERATION CONTROL DEVICE
摘要 PURPOSE:To enable to constitute ultra-high integrated semiconductor elements easily, by using the subtraction means without using comparators to judge the ineffectivity of advanced fetch instruction, when branching is established during the execution of instruction. CONSTITUTION:The means ALU (alithmetic and logic unit) 220 which subtracts the content of the location counter 208 from the content of the memory address register 206, is provided. If the result of subtraction of this subtraction means is 0 or more and less than MXN (where; M is the number of stages of instruction buffer, and N is the number of bytes indicating the capacity of each stage), or if branching is established during the execution of user's instruction, the content of the instruction buffer is made ineffective to replace the content of instruction buffer. This replacement is set in either case above for the flip-flop indicating the advanced fetch in the advance fetch control set and it is done during the reset period.
申请公布号 JPS56118150(A) 申请公布日期 1981.09.17
申请号 JP19800022489 申请日期 1980.02.25
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 KINOSHITA TSUNEO;SATOU FUMITAKA;YAMAZAKI ISAMU
分类号 G06F9/28;G06F9/22;G06F9/38 主分类号 G06F9/28
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