发明名称 NON-VOLATILE SEMICONDUCTOR MEMORY CELL AND DATA ERASE THEREOF
摘要 PURPOSE:To enable low power source voltage operation by forming a region between a floating gate electrode and a control gate electrode of a multilayer insulation film which comprises a silicon oxide film, a silicon nitride film and a silicon oxide film. CONSTITUTION:An erase gate electrode 8 comprising an N type polycrystal silicon layer is formed in a self-matching manner by way of a silicon oxide film/silicon nitride film/silicon oxide film type third gate insulation film 7. In addition, a lower part of a floating gate electrode 6 is partially capacity- bonded by way of a second gate electrode 5 whose structure is identical to that of a control gate 3, thereby constituting a write in/read out transistor of the floating gate electrode 6, the first gate silicon oxide film 4, and source/ drain diffusion layers 14 and 15.
申请公布号 JPH04150072(A) 申请公布日期 1992.05.22
申请号 JP19900274787 申请日期 1990.10.12
申请人 NEC CORP 发明人 IWASA SHOICHI
分类号 G11C17/00;G11C16/04;H01L21/8247;H01L27/115;H01L29/423;H01L29/788;H01L29/792 主分类号 G11C17/00
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