| 摘要 |
<p>PURPOSE:To prevent destruction of insulation film of a selection gate transistor (TR) at repetitive erasure by applying a prescribed potential to a gate of the selection gate TR at the erasure in an EEPROM employing a memory TR having a floating gate and a control gate. CONSTITUTION:A NAND cell type EEPROM is formed with control gate TRs QS1, QS2) and memory TRs M1 - M4 each having a floating gate and a control gate provided on a substrate in series connection. Then in the case of erasure, control gates CG1 - CG4 of the TRs M1 - M4 are brought into 0V, and a high level such as 18V is applied to the substrate to apply 18V to also selection gate lines SG1 - SG2, then electrons of the floating gate of the TRs M1 - M4 are discharged to a P-channel well and a threshold level is moved in the negative direction to apply erasure. Even when the erasure is repeated in the method in which a similar high level to a level fed to the substrate is applied to the gate of the selection gate TR, the destruction of the insulation film of the control gate TR is prevented and the reliability of the EEPROM is enhanced.</p> |
