| 摘要 |
PURPOSE:To ensure an emulation and a sure debugging operation even in a high-speed clock by adding a waiting /latch part provided with a waiting circuit and a latch circuit between a microprocessor and a target system. CONSTITUTION:A D flip-flop DF/F4 serves as a waiting circuit which inputs a bus cycle starting signal 8 as well as a clock signal 11 which samples an external bus cycle end permitting signal 9 between a microprocessor 1 and a target system 29 to a conventional in-circuit emulator and supplies an internal bus cycle end permitting signal 10 to the microprocessor 1. A latch circuit 3 inputs the inverted signal of a read/write signal 7 of the microprocessor 1 as well as the signal 10 to hold the data on the system 29 and supplies the data to the microprocessor 1. Both the DF/F4 and the circuit 3 are added to a waiting/latch part 31. In such a constitution, the system 29 can be surely debugged even in the case of high-speed clock. |
