| 摘要 |
PCT No. PCT/JP89/00129 Sec. 371 Date Nov. 13, 1989 Sec. 102(e) Date Nov. 13, 1989 PCT Filed Feb. 9, 1989 PCT Pub. No. WO89/07825 PCT Pub. Date Aug. 24, 1989.A burst error correction apparatus suitable for correcting burst error due to a bit slip in a self-clocking signal containing resync codes at predetermined intervals, e.g., a self-clocking signal read out from a digital recording medium before the signal is demodulated. This apparatus has a shift register for receiving the self-clocking signal in series; a detector for detecting, an inhibited pattern which has not existed in the self-clocking signal in response to parallel outputs from a section in the vicinity of the entrance of the shift register; and a controller for shifting, by respectively controlling clocks applied to the shift register and a rear stage of the same, data appearing from a position in the vicinity of the inhibited code between adjacent resync codes to the subsequent one of these resync codes in accordance with the direction and the number of bits based on a detection signal from the detection means. The apparatus enables data reading with improved accuracy even in a system inferior in accuracy by correcting burst error due to a bit slip in a self-clocking signal containing resync codes at predetermined intervals before this signal is demodulated, and also enables, with respect to a system improved in accuracy, a reduction in the number of redundant data items for error detection/correction.
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