| 摘要 |
1. Series network arrangement adjustable in stages, consisting of delay sections (ZGm , ZDm , m vepsiln {1, ..., n+1}) and a number of controlled sources (T1 ... Tn ; VCCS), a signal input (E) and a signal output (A) in the manner of a distributed amplifier comprising a delay line in the output circuit, characterized in that a) the controlled sources (VCCS) can be individually optionally connected and disconnected, and in that b) dual-gate FETs (T1 ... Tn ) are used as controlled sources, the first gate (G1 ) of which is in each case connected via delay sections (ZGm ) to the input signal voltage and the second gate (G2 ) of which is in each case connected to suitable direct voltages for connecting or disconnecting the respective FETs.
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