| 摘要 |
A finite impulse response digital filter for a digital communications system has successive virtual taps, the successive virtual taps having tap weight coefficients c1 to c5, respectively, where c1 = c5, c2 = c4, and c3 is the coefficient of a virtual center tap. The filter comprises an add-and-delay multiplier circuit having three physical taps with tap weight coefficients d1, d2 and d3, where d1 = c1 + c2 = c4 + c5, d2 = c2 + c3 = c4 + c3, and d3 = c1 = c5. The circuit comprises tap weight multipliers (1, 2, 3), delay elements (4, 6, 8, 10) connected to the tap weight multipliers to define the physical taps, and adders (5, 7, 9, 11). The arrangement is such that a first digital output sequence comprising d1 x ai-2 + d2 x ai-1 + d3 x ai appears at the output of one of the adders and a second digital output sequence comprising d3 x ai-2 + d2 x ai-1 + d1 x ai appears at the output of another adder, where ai represents a digital sample at a given instant, and ai-1 and ai-2 represent digital samples which are delayed for intervals T and 2T, respectively, with respect to ai, where T is the reciprocal of the symbol rate of digital samples of the communications system. The first and second output sequences are alternately sampled at intervals T and coupled to an output terminal of the digital filter. |
