| 摘要 |
<p>PURPOSE:To generate timing pulses with a wide variable range, by supplying externally adjustable clock pulses to FFs controlled by plural shift registers. CONSTITUTION:Shift registers 10 and 20 shift the 1st clocks 11 and 21 which are supplied externally in response to the same starting signal, and are of the same frequency and out of phase with each other, and then output those clocks, bit by bit. Selecting circuits 30, 40, 50 and 60 compare the numbers and output signals of registers 10 and 20 with prescribed logical values and, when both of them coincide each other, output signals. Logical values 31, 41, 51 and 61 are supplied to the corresponding circuits 30, 40, 50, and 60; and the outputs of the circuits 30 and 40 are sent to an FF70, and those of the circuits 50 and 60 are sent to an FF80. At the same time, the 2nd clocks 71 and 81 of the same frequency synchronizing with the 1st clocks are applied to the FFs 70 and 80 respectively. Thus, leading or trailing edges of pulses are determined to output pulses for timing pulse generation from the FFs 70 and 80.</p> |
