| 摘要 |
PURPOSE:To reduce the memory cell space thereby enhancing the integration by a method wherein the drain regions and resistor elements of a transistor forming multiple bit cells are connected in series while resistor elements are buried-formed in an interlayer insulating film. CONSTITUTION:Gate electrode 4 and an aluminum wiring 12 respectively play the roles of the word wires and the digit wire. Next, the polycrystalline silicon buried layers 7 as resistor elements are connected to the wiring 12 through the intermediary of the first and second WSi layers 8, 11 so that the aluminum may alloy-react to the polycrystalline silicon to prevent the buried layers 7 as the resistor layers from declining or changing. Furthermore, e.g. even if the wiring 12 is disconnected by stress or electromigration, the WSi layers 8, 11 play the role of the digit wires. On the other hand, all of the channel regions are formed in the same size while the layers 7 are buried-formed in an interlayer insulating film 6. Through these procedures, the memory cell space can be reduced to enhance the integration. |
