| 摘要 |
PURPOSE:To reduce the area of a cell by reducing the wiring region between MOS transistors, by dividing each wiring into two-terminal wirings, checking the kinds of both end terminals of the two-terminal wirings, classifying these wirings into prescribed groups, and constituting wiring in a wiring region on a MOS transistor row, from the wiring in a group. CONSTITUTION:The kinds of terminals in a net 1 and a net 2 are checked. The net 1 is a wiring to connect a connecting diffusion layer 161 and a connecting diffusion layer 162. The net 2 is a wiring to connect a gate 81 and a gate 82. Here, wiring selection reference is as follows; (a) two-terminal wiring to connect a connecting diffusion layer and a connecting diffusion layer. (b) two-terminal wiring layer to connect a separating diffusion layer and a connecting diffusion layer, (c) two-terminal wiring to connect a separating diffusion layer and a separating diffusion layer, (d) two-terminal wiring to connect a connecting diffusion layer and a gate, (e) two-terminal wiring to connect a separating diffusion layer and a gate, and (f) two-terminal wiring to connect a gate and a gate. According to the above selection reference, the net 1 is wired in a wiring region 4 on an element row, and the overflowed net 2 is wired in a wiring region 3. |
