| 摘要 |
Two trains of clock pulses in phase opposition are applied to the cascaded stages of the shift register. There are two MIS transistors and resetting is effected by a third MIS transistor which is shunted by a capacitor. A clock pulse rises to a high level, the first transistor is turned on so that the node is driven to a high potential and second transistor is turned on. The first clock pulse falls to a low level and the second clock pulse rises to a high level. Since the second transistor is on, the node is driven to a high level. The second transistor bootstraps the potential of the first node to a higher level.
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