| 摘要 |
PURPOSE:To reduce the chip area by constituting the titled circuit by two P- channel MOS transistors(TRs), two N-channel MOS TRs and 5 inverters. CONSTITUTION:The source of a 1st P-channel MOS TR 2 is connected to an input terminal 1 and the gate is connected to the output of a 1st inverter 11 respectively. The gate of a 1st N-channel MOS TR 3 is connected to the output of a 2nd inverter 7 and the source is connected to a negative power supply 13 respectively and the input 4 of a 3rd inverter 4 is connected to the drain of the 1st N-channel MOS TR 3 and the drain of the 1st P-channel TR 2. Moreover, the 2nd P-channel MOS TR 8 and the N-channel MOS TR 9 are provided. Thus, the chip area is reduced. |
