发明名称 |
Bi-CMOS voltage level conversion circuit |
摘要 |
In the output circuit a signal from an internal circuit is supplied to the gate of an N-channel type MOS transistor, a node of two resistors connected in series across a power supply terminal and ground is connected to one end of the MOS transistor. An NPN transistor is connected at its base to the node, at its collector to the power supply terminal and at its emitter to an output terminal. The positive polarity terminal of a power supply is connected to the power supply terminal to supply a positive voltage VCC and the negative polarity terminal of another power supply is connected through a load resistor to the output terminal to supply a negative voltage.
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申请公布号 |
US4788459(A) |
申请公布日期 |
1988.11.29 |
申请号 |
US19870024164 |
申请日期 |
1987.03.10 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
TSUGARU, KAZUNORI;SUGIMOTO, YASUHIRO |
分类号 |
H03K19/0175;H03K19/018;(IPC1-7):H03K19/092;H03K17/16;H03K19/02;H03K17/60 |
主分类号 |
H03K19/0175 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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