| 摘要 |
PURPOSE:To improve a hit rate, to solve a bus bottle neck and to attain the speed-up of a whole processor by providing a prefetch counter, a cashe address counter and a difference detection circuit which detects the difference between addresses shown by the prefetch counter and the cashe address counter. CONSTITUTION:The prefetch counter 1 executes the fetch of an instruction ahead of an external storage device 17 and the cashe address counter 2 executes the fetch of the instruction to an incorporated cashe memory 5. By providing the difference detection circuit 3 which detects the difference between the prefetch counter 1 and the cashe address counter 2, the prefetch counter 1 and the cashe address counter 2 are activated independently as far as a cashe mishit does not occur when the difference is within a fixed value. When the difference exceeds the fixed value, the action of the prefetch counter 1 is stopped until the difference remains at the fixed value or the cashe mishit occurs. Thus, the high speed microprocessor can be obtained.
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