| 摘要 |
PURPOSE:To perform a processing without waiting a module issuing a bus request for a long time, by enabling the bus to be used again after another one module uses the bus when the bus request is not reset after a prescribed amount of data are transferred. CONSTITUTION:A bus request validity indication circuit 100, when the bus request being still valid after the usage of the bus is permitted and the data transfer of the prescribed amount of data are performed, sets the output at a logic (1) after a bus acknowledge signal is reset. And such output state is transferred in order to the bus request validity indication circuit 100 and a bus request validity indication shift circuit 300 of an another bus usage control circuit 601, and the sending of the bus acknowledge signal is controlled. As a result, when not bus request signal is still reset after the data transfer of the prescribed amount of data in its own module, the usage of the bus after the usage of the bus by another one module is permitted again. |
