| 摘要 |
Memory cell data is read out from memory cell arrays by a column decoder/sense amplifier in a data refresh mode. The data read out by the column decoder/sense amplifier is supplied to a decoding/correction circuit to be subjected to error detection. If an error is detected, the error data is corrected by the correction circuit. The corrected data is again supplied to the column decoder/sense amplifier, and the data held in the column decoder/sense amplifier is rewritten in an original memory cell, thus performing data refresh and error correction operations. In the refresh mode, addresses for selecting memory cells are automatically generated inside a memory device by an internal address generating means consisting of a pulse generator for generating a pulse signal in accordance with a column address strobe signal and a row address strobe signal and of a counter circuit for counting the pulse signal. The data read out in the data read mode is not corrected by the correction circuit. The access time of the memory cells is equal to that of the cells used in conventional memory devices. |
