| 摘要 |
PURPOSE:To decrease parasitic resistance and to prevent the formation of a depletion region in an N<-> layer, in an MISFET having an LDD structure, by providing a conductor layer comprising silicide on the N<-> layer comprising low concentration phosphorus. CONSTITUTION:0n a P-type silicon substrate 11, a gate electrode 14 is provided through a gate insulating film 13. An oxide film 15' is formed by thermal oxidation of the polycrystalline silicon of the gate electrode 14 on the side wall of the electrode 14. A titanium silicide layer 18 on the gate electrode 14 and a titanium silicide layer 19 on a diffused layer are electrically insulated by the film 15'. The Ntype diffused layers of a source and a drain are constituted by the following two parts. Namely, an N<-> layer 20 is formed with low dosed phophorus at the nearest part to a channel. An N<+> diffused layer 22 is formed by a self-aligning ion implantation at a part neighboring the N<-> layer 20 with the gate electrode 14 and a sapcer 21 as masks.
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