发明名称 BURST TIMING SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To reduce the circuit scale by applying an address and an output of a frame counter to a ROM so as to read a corresponding burst timing signal and using a selector conrolled by a control signal thereby selecting only a selected cahnnel burst timing signal. CONSTITUTION:The burst timing signals themselves of all channels are written in a sotrage means 12, plural burst timing signals are read among them, they are selected by a selection means 15 to obtain a set burst timing signal. That is, the address is fed to a storage means 12 together with the output of an F counter 13 in the address and control signal corresonding to the channel set by a CH setting means 14. Then plural burst timing signals corresponding to the address are read while a corresponding F-countr 13 is outputted and the burst timing signal of the channel set by the selection means 15 controlled by a control signal is extracted. Thus, the circuit scale and power consumption reduced.
申请公布号 JPS62299128(A) 申请公布日期 1987.12.26
申请号 JP19860142563 申请日期 1986.06.18
申请人 FUJITSU LTD 发明人 YANO KAZUO
分类号 H04J3/06;H04J3/00 主分类号 H04J3/06
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