| 摘要 |
PURPOSE:To utilize as much as possible the advantages of a fast action mode for partial writing by processing collectively a series of words including that requiring the partial writing in a fast action mode. CONSTITUTION:When a partial writing request is given for the data shown by oblique lines, a memory control signal generating circuit 2 and a memory address generating circuit 3 produce the nipple mode read cycle needed for reading a 4th and 1st word requiring the partial writing. In such case, the lower two bits of an address is continuous to a 1st word '00' from the 4th word '11' and therefore the address of the 4th word is applied first. This address is renewed with the address of the 1st word within a memory device 1 in a single step. These 4th and 1st words read out successively to an RDR in said read cycle are led to a mere control circuit 9 and the non-replacement byte designation information to be written to the byte positions corresponding to the WDR7 and 4 respectively. Thus the perfect group of words to be written to the device 1 is obtained.
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