<p>Logic adder circuit. A logic circuit incorporating carry look-ahead in which substantial savings can be achieved as regards the hardware for generating the sum signals and carry signals by a suitable choice of the adder gate, i.e. by utilizing the already present signal < IMG > which is also used for generating the carry look-ahead signal.</p>
申请公布号
CA1229172(A)
申请公布日期
1987.11.10
申请号
CA19850473774
申请日期
1985.02.07
申请人
N.V.PHILIPS'GLOEILAMPENFABRIEKEN
发明人
VAN MEERBERGEN, JOZEF L.;VEENDRICK, HENDRIKUS J.M.;WELTEN, FRANCISCUS P.J.M.;VAN WIJK, FRANCISCUS J.A.
