| 摘要 |
PURPOSE:To evaluate more practically an operation speed of a multiplier by executing a multiplication to an input test pattern in which almost all of numerical parts xi of a multiplicand X of a prescribed expression are logic '1', and also all of coefficients yj of a multiplier Y are alternate numbers of logic '1' and '0'. CONSTITUTION:In case an input test pattern of an array type multiplying device is expressed by an expression I or an expression II, and an multiplication is executed to an input in which a numerical part xi of a multiplicant X in the expression is logic '1', and a coefficient yj of a numerical part of a multiplier Y is an alternate numerical value of logic '1' and '0', an output of a partial product generator is inputted to a half-adder 20, its output is inputted to a full adder 21, its output is inputted to a full adder 22, and its output is inputted to a CLA adder 23. Logic '0' of the input of the half-adder 20 has been varied to '1', the carry of its output, and the sum become '1' and '0', respectively, and the carry and the sum of the respective outputs of the full adders 21, 22 are varied to '0', '1', and '1', '0', respectively. The adder 23 propagates the carry of each stage, and thereafter, inverts the carry propagation, and propagates a dynamic signal to the longest propagation path. |
