| 摘要 |
PURPOSE:To increase the phase synchronization lock-in speed and to increase the phase synchronization lock-in range by reducing the jitter component in a steady state where the phase difference is small between the input and the output and at the same time increasing the time base control amount in a transient state where said phase difference is large. CONSTITUTION:The cumulative delay signals b2 are supplied continuously to a shift register 14 in case the rise of an output clock pulse has a large delay compared with the rise of the input signal sent from an input signal source 1. Then the continuous delay signal B2' is set at a high level and the 2nd nega tive control signal b3' is applied to a time base control circuit 3 in the first half period. Thus the output clock cycle is set at 16 against 20 of the reference period in a time base control section to perform the control of -4. While with the steady characteristics in the second half period, the continuous advance signal a2' and the delay signal b2' are never set at high levels because the cumulative advance signal a2 and the signal b2 are not deflected to a signal side. Thus the cycle of the output clock is set at 18 or 22 and controlled in a + or -2 range of the reference clock period 20.
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