| 摘要 |
Herein disclosed is a microcomputer system having a peripheral storage control (107) equipped with both a circuit made responsive to a transfer command given from an MPU (101) to set a transfer start address, which is designated subsequent to that command, in a counter (111), which is made operative to give an address for a buffer (110), and to transfer the output of the buffer (110) to a common bus (112) connected between the MPU (101) and an RAM (102), and a circuit (103) for controlling the aforementioned counter (111) to count up in response to a transfer acknowledge signal which is subsequently fed from a direct memory access control (106). In order that the date in the buffer (110) may not be transferred to the RAM (102) but the rewritten, the peripheral storage control (103) is further equipped with both a circuit for setting a rewrite address further given from the MPU (101) in the counter (111) which is operative to give the address of the buffer (110), in association with a rewrite command fed from the MPU (101), and a circuit for giving the rewrite signal to the buffer (110) each time the rewrite data are given after the setting operation from the MPU (101). |
