发明名称 DIGITAL SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To reduce number of components by inserting an isolator on the way of a data line through which a serial signal is sent so as to use only three isolators even when number of signal lines through which a parallel signal is outputted. CONSTITUTION:When a 4-bit signal is inputted sequentially to a shift register 13a via an isolator 6 from a data line 10, the 4-bit signal is shifted at each input of a clock signal 11 and the 4-bit signal is held in the shift register 13a. When one-bit signal is outputted from the data line 10, the signal is shifted to next shift registers 13b, 13c. When data are set to the shift registers 13a-13c, a 4-bit BCD signal is outputted from the shift registers 13a-13c through signal lines 7a-7l by using a strobe signal 12.
申请公布号 JPS6276327(A) 申请公布日期 1987.04.08
申请号 JP19850199581 申请日期 1985.09.11
申请人 CHINO CORP 发明人 NEGISHI HIDEKI;IDA TOSHIKAZU
分类号 H03M9/00 主分类号 H03M9/00
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