发明名称 |
Apparatus and method for testing and verifying the refresh logic of dynamic MOS memories |
摘要 |
The refresh logic of a dynamic MOS memory subsystem of a data processing system is tested by providing apparatus for counting refresh cycles and generating a counter output signal in a first state after a predetermined number of refresh cycles. A microprocessor periodically tests the state of the counter output signal and keeps a count of the number of times the counter output signal was tested and found to be in a second state. When the microprocessor tests and finds the counter output signal in a first state, the microprocessor compares the number of times it tested and found the counter output signal in a second state and determines if that count is within a predetermined range for correct operation.
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申请公布号 |
US4639858(A) |
申请公布日期 |
1987.01.27 |
申请号 |
US19830510711 |
申请日期 |
1983.07.05 |
申请人 |
HONEYWELL INFORMATION SYSTEMS INC. |
发明人 |
MURRAY, JR., THOMAS L.;HOLTEY, THOMAS O. |
分类号 |
G06F12/16;G11C11/401;G11C29/00;G11C29/02;(IPC1-7):G06F13/00;G11C7/00 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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