发明名称 |
METHOD AND CIRCUIT FOR PROVIDING ADJUSTABLE CONTROL OF SHORT CIRCUIT CURRENT THROUGH A SEMICONDUCTOR DEVICE |
摘要 |
Power Field Effect Transistors are commonly used to provide a series conduction path between a source of operating potential (12) and a load (14). A problem occurs if the load should cause the transistor to become a short circuit during which time rush currents across the FET (10) may seriously damage or even destroy the FET. A solution for limiting short circuit current flow in a Field Effect Transistor (10) and to limit the power dissipated therein includes sensing a rise in the drain-to-source voltage of the transistor and clamping the gate-to-source voltage to a predetermined adjustable value thereby reducing the magnitude of the short circuit current flow to within the safe operating characteristics of the device. A comparator switch circuit (32, 36) is responsive to the drain-to-source voltage of the FET exceeding a reference voltage value for clamping the gate-to-source voltage to a predetermined reduced voltage. A trimmable resistive network (40) is connected between the gate and the source electrode of the transistor for adjusting the gate-to-source clamped voltage potential to compensate for variations in transistor transductances from one transistor to the next that may be used in conjunction with the electronic circuitry. |
申请公布号 |
WO8605926(A1) |
申请公布日期 |
1986.10.09 |
申请号 |
WO1986US00274 |
申请日期 |
1986.02.10 |
申请人 |
MOTOROLA, INC. |
发明人 |
BYNUM, BYRON, G.;JARRETT, ROBERT, B. |
分类号 |
H02H9/02;H03K17/082;H03K17/30;(IPC1-7):H02H3/00 |
主分类号 |
H02H9/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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