| 摘要 |
PURPOSE:To decrease the size of an output transistor (TR) by providing a level shifter comprising a CMOS inverter to the pre-stage of a high dielectric strength output buffer and setting a value of a negative power supply to a value between a negative power supply voltage of the final output stage and a common. CONSTITUTION:The level of a terminal 3 is set to positive power terminal voltage VDD=5V of an output stage, a level of a terminal 7 is set to a negative power terminal voltage Vpp=-30V of an output stage, a level of a terminal 11 is set to a negative power terminal voltage Vp of a level shifter in the range of 0>=Vp>=Vpp. Two stages of level shifters operated between VDD and Vp com prising TRs 8, 10 and 12, 14 are provided between an internal signal processing section (pre-stage circuit section including inverter 1) operated by voltage be tween the VDD and the common level and an output buffer 2 operated at a voltage between VDD-Vpp. Thus, the voltage amplitude fed to the gate of the output buffer 2 is increased, the size W of output buffer is reduced and the increase in the power consumption at standby is eliminated.
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