| 摘要 |
PURPOSE:To attain natural movement for even an animation picture by excluding forcibly competition in synchronization with power-on to eliminate the need for deletion or reuse of a required pattern when competition of write/read of a frame synchronizer takes place. CONSTITUTION:A write clock FW on a frame memory 3 is used and a clock FW is compared by a comparator 16, from which a comparison pulse PC is outputted. The pulse width tau of the comparison pulse PC is compared with pulse widths Ta, Tb from a pulse generation circuit 25 by NAND circuits 21N, 22N. As a result, when a write timing is given, only an address control section 22 is actuated and no write address control section 21 is operated. On the other hand, when the write timing is in progress gradually, information for one frame's share is thrown away as a result. Since the 3rd and 4th pulses changed forcibly are fed to the NAND circuits 21N, 22N at power-on, the competition between write and read never takes place for at least several hours.
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