| 摘要 |
<p>PURPOSE:To obtain a memory cell requiring no enhancement type reading transistor by applying the gate bias of an MIS type transistor belonging to a non-selection word line in a direction in which the transistor is not conductive. CONSTITUTION:Gates of memory elements M11, M12, M21, M22 are connected through word lines W1, W2 to a switch 10 and an X decoder 12. Sources of the respective memory elements are connected through bit lines B1, B2 to a switch 14, a drain is connected through a switch 11 controlled by a Y decoder 16 to an input and output circuit 18 during reading, and a well is connected through an S1 to a switch 20. In case of reading the memory elements M11, M12, a word line W1 is set at 3V, a word line W2 at -0V, B1, B2 at 3V, and S1 at -0V. In this manner, without receiving the influence of the memory elements belonging to the non-selecting word lines, the information of the memory element constituted with one element/bit can be read.</p> |
