Bus control gate array.

摘要

In a computer having a central processing unit (CPU) (9), a common bus (1, 3, 5), a plurality of input and output devices which are connected to the common bus (1, 3, 5) and which have an intrinsic I/O device address, individually, and a bus control gate array, the bus control gate array according to the present invention includes an I/O device address decoder (47). The I/O device address decoder 47 comprises a plurality of gates (53, 55...57) and decodes an I/O device address supplied from the CPU (9) to produce a control signal for selecting the designated I/O device thereto.