| 摘要 |
PURPOSE:To obtain an CMOS circuit, which resists a latch-up and is difficult to be broken, by inserting a resistor between a PMOS and a power supply or an NMOS and a grounding or both the power supply and the grounding. CONSTITUTION:A resistor RP connecting a P diffusion region 3 and a power supply terminal 7 is formed. When the voltage of an output terminal 9 exceeds supply voltage, a transistor Q3 is turned ON and currents IRS begin to flow through a resistor RS in operation at that time, but a latch-up is difficult to be generated only by a section corresponding to potential RP.IRP. When the voltage of the output terminal 9 drops to grounding or lower, a transistor Q1 is turned ON, and currents IRS begin to flow through a resistor RW. Even when a transistor Q4 is turned ON, currents flow through the resistor RS and the potential of the output terminal 9 rises to grounding or higher, the latch-up is stopped because a transistor Q2 is not turned ON. |
