PHASE COMPARATOR AND PHASE LOCKED LOOP HAVING SAME

摘要

A phase comparator for receiving an input signal and a signal to be compared with this input signal, comprising an auxiliary stage. The auxiliary or dynamic reducing stage includes a circuit for reducing a predetermined value of the phase difference between the two inputs of the comparator and a circuit for recovering said value at the output of the comparator via a circuit delaying the information expressing this value. The phase comparator may be used in a phase locked loop.