Digital memory color framing circuit

摘要

The invention provides a color framing circuit for a digital memory, which has a first read line flip-flop generator for producing an RLFF0 pulse; a toggle flip-flop for receiving a loading data from a memory using a vertical pulse or a delayed (1H) vertical pulse as a load timing pulse only when the RLFF0 pulse is high and for producing an output signal (RLFF1 pulse); a vertical selector for selecting one of the vertical pulse and the delayed vertical pulse when the output signal from the toggle flip-flop is high; a read address counter for producing an address signal; and a blanking/burst generator for receiving the RLFF0 and RLFF1 pulses as control pulses, thereby receiving as a read address signal the address signal from the address counter. An output video signal phase offset is decreased corresponding to a range of 140 ns (peak-to-peak), and one of the address counters is eliminated.