| 摘要 |
PURPOSE:To reduce a clock oscillation frequency to half by providing the 1st latch circuit which samples a horizontal synchronizing signal with the output of a clock oscillator for synchronism detection and the 2nd latch circuit which also performs sampling with the delayed output of the clock. CONSTITUTION:The output signal of the clock oscillator 2 for synchronism detection is inputted to the CLK terminal of a latch circuit 1 and a delay circuit 3. This circuit 1 latches the horizontal synchronizing signal LSYNC with the leading edge of the clock of the oscillator and supplies an output A to an OR gate 5. On the other hand, the clock signal delayed by the circuit 3 is applied to the CLK terminal of a latch circuit 4 to sample the signal LSYNC with its leading edge, and a signal B is outputted and also inputted to the OR circuit 5. Those outputs A and B are passed through the circuit 5 to generate a synchronism detection output. |
