发明名称 |
LOGIC ANALYZER |
摘要 |
PURPOSE:To execute a trigger when a digital signal has been generated in order by a prescribed pattern, by setting a sequence condition in relation to an input digital signal. CONSTITUTION:Plural digital signals are inputted to an acquisition system part 250 from a data probe 100. In this state, write of the digital signal to a measurement control part 400 is stopped in accordance with a sequence condition set by a CPU800 in relation to the input signal. |
申请公布号 |
JPS6057264(A) |
申请公布日期 |
1985.04.03 |
申请号 |
JP19840048979 |
申请日期 |
1984.03.14 |
申请人 |
YOKOGAWA HIYUURETSUTO PATSUKAADO KK |
发明人 |
JIYOOJI EE HAAGU;OO DAGURASU FUOTSUGU;GOODON EE GURIINREI;SUTEIIBU EE SHIEPAADO;EFU DANKAN TERII |
分类号 |
G01R13/28;G01R31/28;G06F11/22;G06F11/25;G06F17/40 |
主分类号 |
G01R13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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