发明名称 MOS TYPE SILICON INTEGRATED CIRCUIT ELEMENT
摘要 PURPOSE:To block leakage due to the decrease in threshold voltage by the exposure to radiation by a method wherein element isolation gate electrodes are connected to a ground line in the case of an NMOS type transistor, and to a power source line in the case of a PMOS type transistor. CONSTITUTION:NMOS transistors 221 and 223 are provided with gate electrodes 31 and 31 connected to the ground line (VSS) 30, and PMOS type transistors 231 and 233 with gate electrodes 34 and 34 connected to the power source line (VCC) 33, and the elements are isolated by these gate electrodes. Besides, common gates 26... and the gate ends of the gate electrodes 31, 31, 34, 34 are provided with insulation films 35 of the same film thickness as that of the gate insulation film of each transistor, so as not come to contact with the field insulation film. Thereby, the leakage between the source and drain regions due to the inversion of the gate ends can be prevented.
申请公布号 JPS6055641(A) 申请公布日期 1985.03.30
申请号 JP19830163295 申请日期 1983.09.07
申请人 KOGYO GIJUTSUIN (JAPAN) 发明人 HATANO YUTAKA
分类号 H01L27/092;H01L21/82;H01L21/8238;H01L27/10;H01L27/118;H01L29/78 主分类号 H01L27/092
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