发明名称 DELAY LINE CIRCUIT
摘要 PURPOSE:To increase or decrease the amount of delay to an output at both sides by providing a connecting means between an intermediate tap of a delay line and an input terminal and matching and terminating both side ends of the delay line so as to extract an output signal therefrom causing a waveform distortion to be prevented from giving in a propagating signal. CONSTITUTION:Since both side terminals 25, 26 of the delay line 23 of a delay line circuit 20 are matched and terminated, a signal propagated to both the side terminals 25, 26 from the intermediate tap 24 via an input circuit 21 is never reflected thereupon or nearly negligible, if any. Thus, the generation of waveform distortion of the signal is not produced possibly. Further, an impedance when viewed from A' is Z0/2 and the effect by a load capacitance is hardly produced. Since a short-circuit terminal board 22 is moved by changing the position of an intermediate tap 24, the amount of delay of a signal produced at both the side terminals 25, 26 of the delay line 23 is changed so as to be decreased at one side terminal while the delay amount is increased at the other side terminal by means of the connection change to the delay line 23 of the input circuit 21.
申请公布号 JPS59178813(A) 申请公布日期 1984.10.11
申请号 JP19830054204 申请日期 1983.03.30
申请人 FUJITSU KK 发明人 KUBOTA KATSUHISA;ADACHI HIROYUKI
分类号 H03H7/30;H03H7/32;H05K1/00;H05K1/02 主分类号 H03H7/30
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