| 摘要 |
PURPOSE:To operate a write and a read control block independently and to allow plural instructions to share a data buffer by providing an access pipeline with plural data buffers and the write and read control blocks for the buffers. CONSTITUTION:The access pipeline of a vector data processor is provided with data buffers 1 in plural stages and a write address register 2 and a read address register 4 are provided for those buffers 1. Then, +1 stepping circuits 3 and 5 are provided for those registers 2 and 4 to constitute counter circuits for writing and reading, and a write and a read set address are set independently in the counter circuits independently for the writing and reading. Those counter circuits are controlled independently to share the buffers 1 among plural instructions, utilizing the buffers efficiently. |
