发明名称 |
TWO-WIRE BUS-SYSTEM COMPRISING A CLOCK WIRE AND A DATA WIRE FOR INTERCONNECTING A NUMBER OF STATIONS |
摘要 |
A computer system comprises a number of stations which are interconnected by means of a clock bus wire (20) and a data bus wire (22) which both form a wired logic function of the signals generated thereon by the stations (32, 34). During the clock pulses, the signal on the data bus wire is stationary; it may change between the clock pulses. Start and stop conditions are formed by a signal combination between clock bus wire and data bus wire (60 and 62, respectively) which is not permissible in a data stream. If there is more than one master station so that a composite clock signal occurs on the clock bus wire, the clocks of the relevant master stations are each time resynchronized to the actual transitions in the composite clock signal. |
申请公布号 |
DE3163103(D1) |
申请公布日期 |
1984.05.17 |
申请号 |
DE19813163103 |
申请日期 |
1981.10.22 |
申请人 |
N.V. PHILIPS' GLOEILAMPENFABRIEKEN |
发明人 |
MOELANDS, ADRIANUS PETER MARTIN M.;SCHUTTE, HERMAN |
分类号 |
G06F13/00;G06F13/368;G06F13/374;G06F13/38;G06F13/42;H04L7/00;H04L12/00;H04L25/38;H04L29/08;(IPC1-7):G06F3/04 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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