发明名称 |
Distortion reducing circuit in FM receiver |
摘要 |
A distortion reducing circuit in an FM receiver comprises a distortion detector for receiving the output of an FM demodulating circuit. The distortion detector comprises a high pass filter, the output of which is applied to a capacitor so that the same is rapidly charged. The conduction of the transistor is changed as a function of the charge voltage across the capacitor and a high frequency component in the output of the FM demodulating circuit is reduced in association with the conduction of the transistor.
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申请公布号 |
US4416024(A) |
申请公布日期 |
1983.11.15 |
申请号 |
US19800210378 |
申请日期 |
1980.11.26 |
申请人 |
SANYO ELECTRIC CO., INC. |
发明人 |
UGARI, TAKENORI;YANO, YOICHI |
分类号 |
H03G3/20;H03G3/34;H04B1/10;H04B1/16;(IPC1-7):H04B1/10 |
主分类号 |
H03G3/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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