| 摘要 |
<p>A frequency synthesiser of the type having a reference frequency source CPG, frequency reduction means PS which cancels pulses from a frequency to be reduced and a jitter compensation signal circuit arranged to compensate for any jitter in the output frequency that would otherwise be caused by each cancelled cycle. The jitter compensation signal is derived from a jitter-containing pulse train via a d.c. removal circuit DCR and an integrator INT. Additionlly, a perturbation signal is injected by a control device CD which causes pulses to be added to and also to be subtracted, by PA and PS respectively, from the frequency to be reduced, the jitter caused by this addition and subtraction also being compensated for by the compensation signal circuit.</p> |
