发明名称 LOGICAL ELEMENT
摘要 PURPOSE:To obtain a logical element with less power consumption by allowing the operation of a transistor (TR), which is turned on by an input digital signal, to lag the operation of a TR which is turned off. CONSTITUTION:Two time constant circuits consisting of resistances 3 and 4, diodes 5 and 6, capacitors 7 and 8, and resistancea 10 and 11 are connected to input terminals and a bias potential VB. The bias voltage VB is set to an intermediate level between both logical levels ''H'' and ''L'', and therefore the diodes decide on the operation points of the time constant circuits respectively. When an input potential has the level ''H'', one time constant circuit on an n-channel side operates, so the turning-on point of an (n) channel transistor (TR) T1 is delayed. When the input potential has the level ''L'', the turning-on point of a (p) channel TRT2 is delayed to the contrary, so the time when both the TRs turn on during switching is shortened.
申请公布号 JPS585031(A) 申请公布日期 1983.01.12
申请号 JP19810102789 申请日期 1981.07.01
申请人 OKAMURA SHIROU 发明人 OKAMURA SHIROU
分类号 H03K19/0948;H03K19/00 主分类号 H03K19/0948
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