| 摘要 |
PURPOSE:To perform the maintenance of a memory device and improve its reliability by generating, holding and informing an error status signal when the value on an output bus is the one other than an expected value at the time other than the output of a data read out from a memory element. CONSTITUTION:When there is no strobing signal STRB1-N at normal operation, all outputs of open collector gates 2-1-1-2-n are ''1''. If the output of any one of the gates 2-1-2-n is fixed on ''0'', the output of a NAND gate 7 is turned to ''1''. Since the output of an AND gate 10 is ''1'' during the non-strobing signal period, a setting signal is generated on the output of the NAND gate 8 by a clock signal and a flip-flip FF11 is set up. Since a strobing signal STRB inputted to an inverter 9 is synchronized with signals STRB1-STRBN, the FF11 is set up and an error status signal is held and sent to a processor. |
