| 摘要 |
PURPOSE:To obtain an error detection/correction code memory device which can also detect address failure, without increasing the number of bits of a memory, by relating an address parity code to the production in an error detection and correction code. CONSTITUTION:At write-in, apparently 17-bit information which consists of 16-bit of written-in information and one-bit of address parity bit from a parity generating circuit 1 in response to an address, is applied to an error detection and correction code generating circuit 2, and the 16-bit information and the 6-bit error detection and correction code are written in a memory 3. At readout, the 16-bit information from the memory 3, the 6-bit error detection and correction code and the address parity bit from the circuit 1 are applied to an error detection code check and correction circuit 4, where the 1-bit error corresponding to the information is corrected, the 2-bit error is detected as the error, and the 1-bit error corresponding to the address parity error is detected as the address error, allowing to detect address failure without increasing the number of bits. |
