| 摘要 |
PURPOSE:To control a bus so that access request of other CPUs can be achieved instantly after the execution of instructions, by outputting a bus control signal to exclusively possesses a common memory for the time required for the execution of instructions from the CPU. CONSTITUTION:Although a common memory access request signal REQ1 of a CPU1 is outputted as the same as conventional circuits, a common memory access request signal REQ2 of a CPU2 is outputted under the conditions of AND condition between an address coincidence signal RD2 and an access preparation signal RDY2 with an AND circuit 6 and absence of a bus control signal GUARD of CPU1 by an inhibition circuit 8. Thus, the CPU1 can exclusively possess a common memory M with the signal GUARD. The said signal GUARD is set according to the length of the instruction of the CPU1 to assure the common memory access time required for the execution of the instruction of the CPU1. Thus, when the access of the CPU1 is finished, the CPU2 is accessible. |
