| 摘要 |
PURPOSE:To lower the wiring voltage of the insulated gate type semiconductor memory device and the reduce the size thereof by simultaneously forming high density layers at the peripheral edge of a layer arranged separately at least from a substrate and the channel peripheral edge between the layers in the MOS device. CONSTITUTION:The n type Si substrate 11 is covered with an SiO2 film, and an n<+> type layer 14 is formed n the periphery. Then, an SiO2 film is newly formed, the layer 14 is covered thereon, a gate oxide film and a polysilicon floating gate 16 are formed, and impurity is introduced to the gate 16. Further, a polysilicon gate electrode 15b is formed through the SiO2 film 15, is etched, and the substrate is exposed. B is diffused, p<+> type layers 12, 13 are formed with the gate 15b as a conductor, the SiO2 is covered thereon, a window is opened thereat, and aluminum electrodes 12b, 13b are formed thereon. According to this configuration a voltage causing avalanche breakdown is low and the n<+> type layer is formed at the periphery of the FET. Therefore, the expansion of the depletion layer from the drain becomes small. Consequently, it can be integrated, and the writing voltage is also low. |
